Alif Semiconductor /AE512F80F5582AS_CM55_HE_View /USB /DCTL

Test Control. Others: Reserved

0 (Val_0x0): Test mode disabled

1 (Val_0x1): Test_J mode

2 (Val_0x2): Test_K mode

3 (Val_0x3): Test_SE0_NAK mode

4 (Val_0x4): Test_Packet mode

5 (Val_0x5): Test_Force_Enable

USB/Link state change request. Software writes this bit field to issue a USB/Link state change request. A change in this bit field indicates a new request to the controller. If software wants to issue the same request back-to-back, it must write a 0x0 to this bit field between the two requests. The result of the state change request is reflected in the USB/Link State in the DSTS register. These bits are self-cleared on the MAC Layer exiting suspended state. If software is updating other fields of the DCTL register and not intending to force any link state change, then it must write a 0x0 to this field. If the user writes 0x2 to the USB/Link State Change field and 0x1 to RUN/STOP, the link goes to compliance mode. Once you are in compliance, you may alternately write zero and ‘10’ to this field to advance the compliance pattern. ValueRequested USB state transition 8 Remote wakeup request Others: Reserved

Controller Save State (CSS). This command is similar to the USBCMD[CSS] bit in host mode and initiates the save process. When software sets this bit to 0x3, the controller immediately sets the DSTS[SSS] bit to 0x1. When the controller has finished the save process, it sets the DSTS[SSS] bit to 0x0. Note: When read, this field always returns 0x0.

Controller Restore State (CRS). This command is similar to the USBCMD[CRS] bit in Host mode and initiates the restore process. When software sets this bit to 0x1, the controller immediately sets the DSTS[RSS] bit to 0x1. When the controller has finished the restore process, it sets the DSTS[RSS] bit to 0x0. Note: When read, this field always returns 0x0.

L1 Hibernation Enable. Note: If Hibernation is disabled, that is, GCTL[GBLHIBERNATIONEN] = 0x0, this bit is tied to zero.

Keep Connect. Note: If Hibernation is disabled, that is, GCTL[GBLHIBERNATIONEN] = 0x0, this bit is tied to zero.

LPM NYET Threshold. When LPM Errata is enabled: Handshake response to LPM token specified by device application. Response depends on the DCFG[LPMCAP] bit.

1. DCFG[LPMCAP] bit is 0x0: the controller always responds with Timeout (that is, no response).
2. DCFG[LPMCAP] bit is 0x1: the controller responds with an ACK on successful LPM transaction, which requires that all of the following are satisfied:

• There are no PID or CRC5 errors in both the EXT token and the LPM token (if not true, inactivity results in a timeout ERROR).
• No data is pending in the TxFIFO and RxFIFO is empty (else NYET).
• The BESL value in the LPM token is less than or equal to the LPM_NYET_THRES bit field.

HIRD Threshold (HIRD_Thres). The controller asserts output signals utmi_l1_suspend_n and utmi_sleep_n on the basis of this signal. The controller asserts utmi_l1_suspend_n to put the PHY into Deep Low-Power mode in L1 when both of the following are true:

• HIRD value is greater than or equal to the value of bits 3-1 in the DCTL[HIRDTHRES] bit field and the value of bit 4 in the DCTL[HIRDTHRES] is set to 0x1. The controller asserts utmi_sleep_n on L1 when one of the following is true:
• If the HIRD value is less than the value of bits 3-1 in the DCTL[HIRDTHRES] bit field or the value of bit 4 in the DCTL[HIRDTHRES] is set to 0x0.

Core Soft Reset. Resets the all clock domains as follows: This bit clears the interrupts and all the CSRs except the GSTS, GSNPSID, GUID, GUSB2PHYCFG0, DCFG, DCTL, DEVTEN, and DSTS registers. All module state machines (except the SoC Bus Slave Unit) are reset to the IDLE state, and all the TxFIFOs and the RxFIFO are flushed. Any transactions on the SoC bus Master are terminated as soon as possible, after gracefully completing the last data phase of a SoC bus transfer. Any transactions on the USB are terminated immediately. Note: Programming this field with random data causes side effect. Bit Bash register testing is not recommended.

Run/Stop. The software writes 0x1 to this bit to start the device controller operation. To stop the device controller operation, the software must remove any active transfers and write 0x0 to this bit. When the controller is stopped, it sets the DSTS[DEVCTRLHLT] bit when the controller is idle and the lower layer finishes the disconnect process. This bit must be used in following cases as specified:

• After power-on reset and CSR initialization, the software must write 0x1 to this bit to start the device controller. The controller does not signal connect to the host until this bit is set.
• The software uses this bit to control the device controller to perform a soft disconnect. When the software writes 0x0 to this bit, the host does not see that the device is connected. The device controller stays in the disconnected state until the software writes 0x1 to this bit. The minimum duration of keeping this bit cleared is specified in the Note below. If the software attempts a connect after the soft disconnect or detects a disconnect event, it must set the ULSTCHNGREQ bit field to 0x5 before reasserting the RUN_STOP bit.
• When the USB or Link is in a lower power state and the Two Power Rails configuration is selected, software writes 0x0 to this bit to indicate that it is going to turn off the Core Power Rail. After the software turns on the Core Power Rail again and re-initializes the device controller, it must set this bit to start the device controller. For more details, see Section Low Power Operation of Controller. Note: The following is the minimum duration for which the soft disconnect (SftDiscon) bit must be set for the USB host to detect a device disconnect. 10 ms:

1. For high-speed, when the device state is Suspended, Idle, or not Idle/Suspended (performing transactions).
2. For full-speed/low-speed, when the device state is Suspended, Idle, or not Idle/Supended (performing transactions).